The design and implementation of double-precision multiplier in a first-generation CELL processor

• Published in: 2005 International Conference on Integrated Circuit Design and Technology, 2005. ICICDT 2005 pp. 11 - 14
• Main Authors: Kuang, J.B., Buchholtz, T.C., Dance, S.M., Warnock, J.D., Storino, S.N., Wendel, D., Bradley, D.H.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2005
• Subjects: Circuits; Clocks; Delay; Laboratories; Latches; Logic design; Scalability; Space vector pulse width modulation; Streaming media; Wires
• ISBN: 9780780390812; 0780390814
• ISSN: 2381-3555; 2691-0462
• DOI: 10.1109/ICICDT.2005.1502577

We present the double precision multiplier for a 90nm PD-SOI first-generation CELL processor. Dynamic booth logic is designed for scalability and with noise, leakage, and pulse width variation tolerance. Static partial product compression is implemented with replicated bits for performance. The design supports fine-grained clock gating domains for active power reduction.