One Micron Damascene Redistribution for Fan-Out Wafer Level Packaging using a Photosensitive Dielectric Material

• Published in: 2018 IEEE 20th Electronics Packaging Technology Conference (EPTC) pp. 395 - 400
• Main Authors: Flack, Warren W., Hsieh, Robert, Nguyen, Ha-Ai, Slabbekoorn, John, Suhard, Samuel, Miller, Andy, Hiro, Akito, Ridremont, Romain
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-12-2018
• Subjects: Dielectric materials; Dielectrics; Lithography; Numerical analysis; Polymers; Resistors; Silicon
• DOI: 10.1109/EPTC.2018.8654363

This study investigates creation of 1.0μm RDL structures by a damascene process utilizing a photosensitive permanent dielectric material. The advantage of the photosensitive dielectric approach is that the Cu overburden removal does not affect the quality of the embedded Cu lines. In comparison, for a semi-additive process the Cu seed etch affects the final dimensions of the RDL lines [1]. Damascene processing of RDL will also result in a flat wafer surface which greatly improves the lithographic performance for subsequent layers. Finally, the Cu line is surrounded on the sides and bottom by a Ti barrier layer which provides a Cu diffusion barrier for enhanced reliability [2,3]. The completed 1.0μm RDL damascene process is evaluated using a test chip design that includes metrology structures for in-line monitoring and CDSEM measurements, and comb and serpentine electrical test structures. The electrical results for the damascene process show significant advantages compared to the semi-additive process.