Process development of multi-layer stacked chip module

Process development of multi-layer stacked chip module

In this paper, at first electroplating of copper and tin is optimized to fabricate micro-bump. Chip-to-chip bonding process is developed. Then, a temporary bonding process is developed and verified by experiment. And finally, a process for manufacturing multiple layer stacked chip module is designed...

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Bibliographic Details
Published in:2011 12th International Conference on Electronic Packaging Technology and High Density Packaging pp. 1 - 3
Main Authors: Shenglin Ma, Xin Sun, Yunhui Zhu, Wenping Kang, Qinghu Cui, Min Miao, Jin Chen, Yufeng Jin
Format: Conference Proceeding
Language:English
Published: IEEE 01-08-2011
Subjects:
Bonding
Copper
Packaging
Silicon
Stacking
Through-silicon vias
Tin
Online Access:Get full text
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Summary:In this paper, at first electroplating of copper and tin is optimized to fabricate micro-bump. Chip-to-chip bonding process is developed. Then, a temporary bonding process is developed and verified by experiment. And finally, a process for manufacturing multiple layer stacked chip module is designed and prototype of a 4 layer stacked chip module is fabricated successfully.
ISBN:1457717700
9781457717703
DOI:10.1109/ICEPT.2011.6066802