Waveform Analysis and Delay Prediction in Simultaneously Switching CMOS Gate Driven Inductively and Capacitively Coupled On-Chip Interconnects

• Published in: 2007 6th IEEE Dallas Circuits and Systems Workshop on System-on-Chip pp. 1 - 4
• Main Authors: Kaushik, B.K., Sarkar, S., Agarwal, R.P., Joshi, R.C.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-11-2007
• Subjects: Analytical models; Coupled mode analysis; Couplings; Delay effects; Delay estimation; Power transmission lines; Propagation delay; Semiconductor device modeling; Shape; SPICE
• ISBN: 1424416795; 9781424416790
• DOI: 10.1109/DCAS.2007.4433215

This paper focuses on waveform analysis and delay estimation of a CMOS gate driven capacitively and inductively coupled interconnect for simultaneously switching inputs. A transmission line based coupled model of interconnect is used for analysis. Delays at far-end of victim are estimated for the conditions when the inputs to two coupled interconnects are switching in-phase and out-of-phase. Alpha Power Law model of MOS-transistor is used to represent the transistors in CMOS-driver. The comparison of analytically obtained results with SPICE simulations show that the proposed model captures 90% propagation delay; transition time delay and waveform shape with good accuracy.