High speed fixed point DSOGI PLL implementation on FPGA for synchronization of grid connected power converters

• Published in: 2014 IEEE 23rd International Symposium on Industrial Electronics (ISIE) pp. 1372 - 1377
• Main Authors: Cossutta, Pablo, Aguirre, Miguel Pablo, Engelhardt, Mathías Angelico, Cao, Andres, Valla, María Inés
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-06-2014
• Subjects: Algorithm design and analysis; Field programmable gate arrays; Inverters; MATLAB; Phase locked loops; Synchronization; Transforms
• ISSN: 2163-5137
• DOI: 10.1109/ISIE.2014.6864814

Power converters are the subject of extensive research because of their ability to work under different operating conditions, providing bidirectional power flow, high dynamic range and fast response. These advantages allow them to be used as an interface between the electric grid and many high power applications such as motors, energy storage, active filters and renewable energy sources. To be able to connect to the utility grid, every power converter must be provided with a synchronization method. The synchronization algorithms are mostly based on the well known Synchronous Reference Frame Phase Locked Loop (SRF-PLL) plus some pre-filter stage that can be achieved by different algorithms of variable complexity, usually implemented on Digital Signal Procesors (DSP) or Microcontrollers. In this paper a simple and highly effective Field Programable Gate Array (FPGA) implementation of a Phase Locked Loop (PLL) algorithm based on a Dual Second Order Generalized Integrator PLL (DSOGI-PLL) is presented in detail, along with the auxiliary circuitry needed to acquire the grid voltage information. Using a fast-prototype high-level synthesis tool, design time is drastically reduced without the need of any Hardware Description Language (HDL) code. Both simulation with MATLAB Simulink and experimental results on a Xilinx FPGA, show a robust behaviour even against frequency steps, severe distortion and unbalances in the power input.