The architecture and the technology characterization of an FPGA-based customizable Application-Specific Vector Processor

• Published in: 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) pp. 62 - 67
• Main Authors: Sykora, J., Kohout, L., Bartosinski, R., Kafka, L., Danek, M., Honzik, P.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-04-2012
• Subjects: Clocks; Computer architecture; Custom accelerators; DSP; Field programmable gate arrays; FPGA; Graphics processing unit; Pipeline processing; Registers; vector processing; Vectors
• ISBN: 9781467311878; 1467311871
• DOI: 10.1109/DDECS.2012.6219026

The traditional approach to IP core design is to use simulations with test vectors. This is not feasible when dealing with complex function cores such as the Image Segmentation case-study algorithm in this paper. An algorithm developer needs to carry out experiments on large real-world data sets, with fast turn-around times, and in real time to facilitate performance tuning and incremental development. We propose a methodology called Application-Specific Vector Processor (ASVP). The ASVP approach first constructs a programmable architecture customized for a given application, then employs software techniques to develop firmware that implements the algorithm. Our sample implementation that supports the Image Segmentation kernel is capable of 332 MFLOPs, 400 MFLOPs, and 250 MFLOPs per coprocessor core in Virtex 5, Virtex 6 and Spartan 6 technologies, respectively. The core size is roughly 1500 slices, depending on the configuration and technology.