Design and Analysis of Wallace Tree Multiplier for CMOS and CPL Logic

Design and Analysis of Wallace Tree Multiplier for CMOS and CPL Logic

In this paper we have designed and analysed Wallace Tree Multiplier for CMOS and CPL Logics. CPL Logic is low power logic. This paper aims at comparing the area, power and delay of Wallace Tree Multiplier for CMOS and CPL Logics. The design is implemented using HSPICE for 180nm Technology. Wallace T...

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Bibliographic Details
Published in:2018 International Conference on Computation of Power, Energy, Information and Communication (ICCPEIC) pp. 006 - 010
Main Authors: Nagaraj, S., Thyagarajan, K., Srihari, D., Gopi, K.
Format: Conference Proceeding
Language:English
Published: IEEE 01-03-2018
Subjects:
3:2 compressors
4:2 compressors
5:2 compressors
Adders
CMOS
CMOS technology
Complementary Pass Transistor Logic(Cpl)
Compressors
Delays
Logic gates
MOSFET
Wallace Tree Multipliier
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Summary:In this paper we have designed and analysed Wallace Tree Multiplier for CMOS and CPL Logics. CPL Logic is low power logic. This paper aims at comparing the area, power and delay of Wallace Tree Multiplier for CMOS and CPL Logics. The design is implemented using HSPICE for 180nm Technology. Wallace Tree Multiplier was designed for 8-bit and 16-bit using 3:2,4:2 and 5:2 compressors.
ISSN:2576-9065
DOI:10.1109/ICCPEIC.2018.8525224