Nonvolatile 3D-FPGA with monolithically stacked RRAM-based configuration memory

• Published in: 2012 IEEE International Solid-State Circuits Conference pp. 406 - 408
• Main Authors: Young Yang Liauw, Zhiping Zhang, Wanki Kim, Gamal, A. E., Wong, S. S.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-02-2012
• Subjects: CMOS integrated circuits; Field programmable gate arrays; Programming; Random access memory; Resistance; Routing; Tiles
• ISBN: 1467303763; 9781467303767
• ISSN: 0193-6530; 2376-8606
• DOI: 10.1109/ISSCC.2012.6177067

SRAM based configuration memory is the primary contributor to the large area, delay, and power consumption of FPGAs relative to ASICs. In [1] it is estimated that a 3D-FPGA with the configuration memory stacked on top of the FPGA logic and routing can achieve 57% smaller die area than a baseline 2D-FPGA in 65nm CMOS technology. Motivated by these potential performance gains, several programmable logic devices with different monolithically stacked configuration memory technologies have been reported [2-4]. These memory technologies, however, require materials and/or processes that may not be compatible or scalable with CMOS processes. This paper presents the first 3D-FPGA with stacked configuration memory based on the emerging nonvolatile Resistive RAM (RRAM) technology described in [5], which is both compatible and scalable with CMOS.