A Reduced Power MUX in 16Nm CMOS Technology

A Reduced Power MUX in 16Nm CMOS Technology

A new 2:1 mux in 16nm cmos design, nmux, is presented in this paper. The proposed design uses dual assignment of threshold voltage and oxide width with a specific pattern. Static power, delay and PDP of nmux is compared with high performance application and low power application multiplexer. It is f...

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Bibliographic Details
Published in:2018 8th International Conference on Cloud Computing, Data Science & Engineering (Confluence) pp. 838 - 841
Main Authors: Singhal, Smita, Mehra, Anu
Format: Conference Proceeding
Language:English
Published: IEEE 01-01-2018
Subjects:
Dual Oxide
dual threshold
gate leakage
Leakage currents
Logic gates
MOS devices
multiplexer
Multiplexing
Performance evaluation
Power dissipation
static power
subthreshold leakage
Threshold voltage
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Summary:A new 2:1 mux in 16nm cmos design, nmux, is presented in this paper. The proposed design uses dual assignment of threshold voltage and oxide width with a specific pattern. Static power, delay and PDP of nmux is compared with high performance application and low power application multiplexer. It is found that there is an improvement of 65.5% in static power and 63.4% in delay as compared to the multiplexer designed for low power applications. Static power in case nmux is reduced to 99.9% as compared to mux designed for high performance applications. The performance of nmux here is reduced to 5.3%. There is no loss in area in proposed mux.
DOI:10.1109/CONFLUENCE.2018.8442637