Improving the Cell Characteristics Using Low-k Gate Spacer in 1Gb NAND Flash Memory

Improving the Cell Characteristics Using Low-k Gate Spacer in 1Gb NAND Flash Memory

Floating gate interference resulting from capacitive coupling through parasitic capacitors surrounding the floating gate degrades the cell characteristics such as current, speed and cell V th distribution. For the first time, we have introduced the cell characteristics improved using low-k dielectri...

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Bibliographic Details
Published in:2006 International Electron Devices Meeting pp. 1 - 4
Main Authors: Kang, D., Jang, S., Lee, K., Kim, J., Kwon, H., Lee, W., Park, B.G., Lee, J.D., Shin, H.
Format: Conference Proceeding
Language:English
Published: IEEE 01-12-2006
Subjects:
Capacitors
Degradation
Dielectrics
Dry etching
Interference
Nonvolatile memory
Parasitic capacitance
Random access memory
Silicon compounds
Voltage control
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Summary:Floating gate interference resulting from capacitive coupling through parasitic capacitors surrounding the floating gate degrades the cell characteristics such as current, speed and cell V th distribution. For the first time, we have introduced the cell characteristics improved using low-k dielectric of gate spacer such as oxide and air gap in 1Gb NAND flash memory
ISBN:142440438X
9781424404384
ISSN:0163-1918
2156-017X
DOI:10.1109/IEDM.2006.346956