Characterization of radiation-induced SRAM and logic soft errors from 0.33V to 1.0V in 65nm CMOS

• Published in: Proceedings of the IEEE 2014 Custom Integrated Circuits Conference pp. 1 - 4
• Main Authors: Pawlowski, Robert, Crop, Joseph, Cho, Minki, Tschanz, James, De, Vivek, Fairbanks, Thomas, Quinn, Heather, Borkar, Shekhar, Chiang, Patrick Yin
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-09-2014
• Subjects: CMOS integrated circuits; Error analysis; Integrated circuit modeling; Inverters; logic; memory; near-threshold; Neutrons; Random access memory; reliability; soft errors
• ISSN: 0886-5930; 2152-3630
• DOI: 10.1109/CICC.2014.6946138

This work details a process-portable test chip, fabricated in 65nm CMOS, specifically designed to measure radiation-induced soft error rate (SER) during operation at near-threshold. A variety of SRAM, register file (RF), and digital logic test structures are included that provide a comprehensive assessment of circuit sensitivities to radiation at low V DD . Neutron irradiation measurements of SRAM/RF show a 6.45x increase in SER when V DD is lowered from 1.0V to 0.33V, and a 2.6x increase in multi-bit upsets. Alpha bombardment of digital logic tests demonstrates the effectiveness of this test chip platform in characterizing the relationship between SER and different circuit characteristics when operating at low V DD .