3-D TCAD Study of the Implications of Channel Width and Interface States on FD-SOI Z2-FETs

• Published in: IEEE transactions on electron devices Vol. 66; no. 6; pp. 2513 - 2519
• Main Authors: Navarro, C., Navarro, S., Marquez, C., Padilla, J. L., Galy, P., Gamiz, F.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-06-2019; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: 1T-DRAM; 3-D; CAD; capacitor-less; Computer aided design; Computer simulation; Dynamic random access memory; dynamic random access memory (DRAM); Electrostatics; fully depleted; Interface states; Logic gates; Mathematical model; memory; Random access memory; Shape memory; Silicon; silicon-on-insulator (SOI); SOI (semiconductors); trap; variability; Variation; Z²-FET
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2019.2912457

3-D numerical technology computer-aided design simulations, based on experimental results, are performed to study the origin of the large Z 2 -FET dynamic random access memory (DRAM) memory cell-to-cell variability on fully depleted silicon-on-insulator (FD-SOI) technology. The body width, cross section shape, and the passivation-induced lateral and top interface state density impacts on the device dynamic memory operation are investigated. The width and body shape arise as marginal metrics not strongly inducing fluctuations in the device triggering conditions. However, the interface state (<inline-formula> <tex-math notation="LaTeX">{D}_{\text {it}} </tex-math></inline-formula>) control, especially at the top of the ungated section, emerges as the main challenge since traps significantly increase the ON-voltage variability threatening the capacitor-less DRAM operation.