Design of domino CMOS cells under delay constraint

Simple expressions to estimate the delay and power consumption of domino gates have been developed. Using these expressions design guidelines are established for domino cells under a specified delay. It has been found that there is a trade-off between the power consumption and noise margin for domin...

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Bibliographic Details

Published in:	Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303) pp. 106 - 109
Main Authors:	Zamudio, A., Champac, V.H., Sarmiento-Reyes, A.
Format:	Conference Proceeding
Language:	English
Published:	IEEE 1999
Subjects:	Capacitance CMOS logic circuits Delay estimation Energy consumption Feedback Logic design Logic devices Logic gates MOS devices MOSFETs
Online Access:	Get full text
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