Design of domino CMOS cells under delay constraint

• Published in: Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303) pp. 106 - 109
• Main Authors: Zamudio, A., Champac, V.H., Sarmiento-Reyes, A.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 1999
• Subjects: Capacitance; CMOS logic circuits; Delay estimation; Energy consumption; Feedback; Logic design; Logic devices; Logic gates; MOS devices; MOSFETs
• ISBN: 9780780355880; 0780355881
• DOI: 10.1109/MMICA.1999.833610

Simple expressions to estimate the delay and power consumption of domino gates have been developed. Using these expressions design guidelines are established for domino cells under a specified delay. It has been found that there is a trade-off between the power consumption and noise margin for domino cells designed for a specified delay. A good correspondence exists between the theoretical and simulated results.