A backside via process for thermal resistance improvement demonstrated using GaAs HBTs

• Published in: GaAs IC Symposium Technical Digest 1992 pp. 267 - 270
• Main Authors: Kofol, J.S., Lin, B.J.F., Mierzwinski, M., Kim, A., Armstrong, A., Van Tuyl, R.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 1992
• Subjects: Biomembranes; Electrical resistance measurement; Etching; Gallium arsenide; Gold; Heterojunction bipolar transistors; Particle measurements; Semiconductor device modeling; Temperature; Thermal resistance
• ISBN: 9780780307735; 0780307739
• DOI: 10.1109/GAAS.1992.247272

The authors report a method for reducing the operating temperatures of GaAs-AlGaAs heterojunction bipolar transistors (HBTs) to acceptable levels, while maintaining the compact device layout needed for high-frequency operation. A structure called backside thermal via is formed by selectively etching nearly all of the GaAs from the back side of the wafer in photolithographically patterned regions, directly under the heat sources, until a five-micron membrane of GaAs remains. Gold is then plated onto the membrane. For one particular transistor design, a greater than 50% reduction of the thermal resistance has been measured. Models suggest that even greater improvement in thermal properties will be obtained as device active area increases.< >