Virtual test with VHDL-AMS for a generator of analog and mixed signal virtual components

• Published in: 1999 Fall VIUF Workshop (Cat. No.PR00465) pp. 88 - 93
• Main Authors: Babba, B., Barret, G., Poullet, F.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 1999
• Subjects: Signal generators; Testing
• ISBN: 0769504655; 9780769504650
• DOI: 10.1109/VIUF.1999.801984

With the increase in the complexity of systems with mixed-signal components, many systems designers recognize advantages and necessity of the mixed-signal simulation of these systems as a whole. Unfortunately, modeling and simulating such complex systems takes an enormous amount of time. The first problem identified is the speed of analog simulation. The second problem is how difficult it is to write accurate and rapid models of a complex analog and mixed-signal system. Mixed-signal EDA tools has arguably, made significant improvement over the past two years. Finally, with the Analog and Mixed Signal HDL standard (VHDL-AMS), accurate and rapid model of a complex electronic system is made possible. This paper presents a case study; the Virtual Test of a virtual component (VC) "ADMIR", a flexible analog to digital converter. The power of VHDL-AMS language makes it possible to write models with different abstraction level of the test chip and the "testboard" of ADMIR.