Memory exploration utilizing scheduling effects in high-level synthesis

• Published in: 2002 IEEE International Symposium on Circuits and Systems (ISCAS) Vol. 4; p. IV
• Main Authors: Jaewon Seo, Thewhan Kim
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2002
• Subjects: Algorithm design and analysis; Clocks; Computer science; Costs; Filters; High level synthesis; Information technology; Libraries; Processor scheduling; Read-write memory
• ISBN: 9780780374485; 0780374487
• DOI: 10.1109/ISCAS.2002.1010391

In this paper, we address one critical limitation of the previous work on the problem of memory exploration in high-level synthesis, namely, a tight coupling of scheduling effects with memory exploration, that has been ignored by most existing memory synthesis systems. To overcome the limitation, we propose an integrated approach that takes into account the memory configurations and schedules simultaneously. Experimental data on a set of benchmark filter designs are provided to show the effectiveness of the proposed exploration strategy in finding close-to-optimal memory configurations.