Orthogonal chip mount - A 3D hybrid wafer scale integration technology

• Published in: 1987 International Electron Devices Meeting pp. 104 - 106
• Main Authors: Malhi, S.D.S., Davis, H.E., Stierman, R.J., Bean, K.E., Driscoll, C.C., Chatterjee, P.K.
• Format: Conference Proceeding
• Language: English
• Published: IRE 1987
• Subjects: Diodes; Integrated circuit interconnections; Integrated circuit technology; Packaging; Process design; Resistors; Silicon carbide; Testing; Thermal conductivity; Wafer scale integration
• DOI: 10.1109/IEDM.1987.191360

In the last decade, device scaling in the integrated circuit technology has permitted a drastic improvement in the density of electronic systems. This trend will continue in the next decade. However, submicron feature sizes involved will demand escalating investment in manufacturing equipment and facilities. MOS technology will also reach its fundamental scaling limit at around 0.2 µm. At this time it is necessary that alternative schemes of system density improvement, which are more cost-effective, be explored. Three-dimensional (3D) hybrid wafer scale integration technologies offer this possibility. Such a novel approach, called Orthogonal Chip Mount (OCM), is introduced and described in this paper.