A comparative analysis of high-speed digital test techniques

A comparative analysis of high-speed digital test techniques

Testing of high performance integrated circuits is becoming increasingly a challenging task owing to higher clock frequencies and non availability/economical of VLSI testers. We outline a DFT strategy such that high performance devices can be tested on relatively low performance testers. Various imp...

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Bibliographic Details
Published in:Engineering Solutions for the Next Millennium. 1999 IEEE Canadian Conference on Electrical and Computer Engineering (Cat. No.99TH8411) Vol. 1; pp. 379 - 384 vol.1
Main Authors: Sachdev, M., Shashaani, M.
Format: Conference Proceeding
Language:English
Published: IEEE 1999
Subjects:
Circuit testing
Clocks
Costs
Frequency
Integrated circuit testing
Logic testing
Manufacturing
Ring oscillators
Timing
Very large scale integration
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Summary:Testing of high performance integrated circuits is becoming increasingly a challenging task owing to higher clock frequencies and non availability/economical of VLSI testers. We outline a DFT strategy such that high performance devices can be tested on relatively low performance testers. Various implementation aspects of this technique are also addressed.
ISBN:0780355792
9780780355798
ISSN:0840-7789
2576-7046
DOI:10.1109/CCECE.1999.807228