Design of a systolic coprocessor for rational addition

• Published in: Proceedings The International Conference on Application Specific Array Processors pp. 282 - 289
• Main Author: Jebelean, T.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 1995
• Subjects: Coprocessors; Digital arithmetic; Equations; Europe; Field programmable gate arrays; Hardware; Mathematics; Polynomials; Reduced instruction set computing; Timing
• ISBN: 9780818671098; 0818671092
• ISSN: 1063-6862
• DOI: 10.1109/ASAP.1995.522932

We design a systolic coprocessor for the addition of signed normalized rational numbers. This is the most complicated rational operation: it involves GCD, exact division, multiplication and addition/subtraction. In particular the implementation of GCD and exact division improve significantly (2 to 4 times) previously known solutions. In contrast to the traditional approach, all operations are performed least-significant digits first. This allows bit-pipelining between partial operations at reduced area-cost. An Atmel FPGA design for 8-bit operands consumes 730 cells (3,500 equivalent gates) and runs at 25 MHz (5 MHz after layout). For 32-bit operands this would be in the same timing range as the software solutions, however a significant speed-up can be expected for longer operands because the linear time-complexity of the hardware algorithms.