System, process, and design implications of a reduced supply voltage microprocessor

• Published in: 1990 37th IEEE International Conference on Solid-State Circuits pp. 48 - 49
• Main Authors: Allmon, R., Benschneider, B., Callander, M., Chao, L., Dever, D., Farrell, J., Fitzgerald, N., Grodstein, J., Hassoun, S., Hudepohl, L., Kravitz, D., Lundberg, J., Marcello, R., Marino, S., Pickholtz, J., Preston, R., Richesson, M., Samudrala, S., Sanders, D.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 1990
• Subjects: Circuits; Clocks; CMOS process; Microprocessors; MOS devices; Oscillators; Process design; Resistors; Tin; Voltage
• DOI: 10.1109/ISSCC.1990.110123

The system, process, and design implications of converting a microprocessor chip set originally implemented in a 5-V, 1.5- mu m (drawn) CMOS process to one implemented in a 3.3-V, 1.0- mu m (drawn) CMOS process are described. The chip set is 75% faster than the previous generation and comprises a processor chip, a floating-point chip, a cache controller chip, and a clock chip. It operates at 62.5 MHz under worst-case conditions. Micrographs of each design are given. Power and packaging specifications for each chip and the 3.3-V, 1.0- mu m (drawn) process specifications are tabulated. A high-temperature schmoo plot for the CPU chip is also given.< >