Correlation of logical failures to a suspect process step

• Published in: International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034) pp. 458 - 466
• Main Authors: Balachandran, H., Parker, J., Shupp, D., Butler, S., Butler, K.M., Force, C., Smith, J.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 1999
• Subjects: Failure analysis; Graphics; Instruments; Logic testing; Manufacturing processes; Monitoring; Performance evaluation; Production; Semiconductor device manufacture; System-on-a-chip
• ISBN: 0780357531; 9780780357532
• ISSN: 1089-3539; 2378-2250
• DOI: 10.1109/TEST.1999.805768

Traditional yield enhancement efforts have long relied on memory bitmapping techniques. With the industry marching toward system-on-a-chip technology, the importance of logic products has increased exponentially. This necessitates the development of innovative techniques to perform logic yield enhancement. In this paper the authors present a novel technique that can be used to perform logic yield enhancement. The paper concentrates on logic bitmapping at Texas Instruments. Results obtained from a few production samples of a graphics processor are also presented.