A new approach for computation of timing jitter in phase locked loops

A new approach for computation of timing jitter in phase locked loops

A new method for computation of timing jitter in a PLL is proposed. The computational method is based on the representation of the circuit as a linear time-varying system with modulated stationary noise models, spectral decomposition of stochastic process and decomposition of noise into orthogonal c...

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Bibliographic Details
Published in:Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537) pp. 345 - 349
Main Authors: Gourary, M.M., Rusakov, S.G., Ulyanov, S.L., Zharov, M.M., Gullapalli, K.K., Mulvaney, B.J.
Format: Conference Proceeding
Language:English
Published: IEEE 2000
Subjects:
Analysis of variance
Chirp modulation
Circuit noise
Differential equations
Noise level
Performance analysis
Phase locked loops
Phase noise
Timing jitter
Transient analysis
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Summary:A new method for computation of timing jitter in a PLL is proposed. The computational method is based on the representation of the circuit as a linear time-varying system with modulated stationary noise models, spectral decomposition of stochastic process and decomposition of noise into orthogonal components i.e. phase and amplitude noise. The method is illustrated by examples of jitter computation in PLLs.
ISBN:9780769505374
0769505376
DOI:10.1109/DATE.2000.840294