A modular 1 mu m CMOS single polysilicon EPROM PLD technology

A modular 1 mu m CMOS single polysilicon EPROM PLD technology

The authors describe a single-polysilicon CMOS process that has been optimized for the production of high-speed programmable logic devices (PLDs). The process departs from conventional approaches in two respects: it is a modular addition to a standard CMOS logic process, and it uses a single-polysil...

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Bibliographic Details
Published in:Technical Digest., International Electron Devices Meeting pp. 60 - 63
Main Authors: Cacharelis, P.J., Hart, M.J., Manley, M.H., Frake, S.O., Knecht, M.W.
Format: Conference Proceeding
Language:English
Published: IEEE 1988
Subjects:
Auditory implants
CMOS logic circuits
CMOS process
CMOS technology
EPROM
Libraries
Nonvolatile memory
Oxidation
Programmable logic devices
Seals
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Summary:The authors describe a single-polysilicon CMOS process that has been optimized for the production of high-speed programmable logic devices (PLDs). The process departs from conventional approaches in two respects: it is a modular addition to a standard CMOS logic process, and it uses a single-polysilicon EPROM cell. The technology has been used to fabricate a 22F10 PLD with an access time of 9.0 ns. Snap-back has been identified as the major cause of program disturb.< >
ISSN:0163-1918
2156-017X
DOI:10.1109/IEDM.1988.32750