Dielectric Stack Optimization for Die-level Warpage Reduction for Chip-to-Wafer Hybrid Bonding

Chip-to-wafer hybrid bonding is a promising packaging technology for bumpless and high-density interconnection. However, this approach presents numerous challenges during die stacking, one of them is the die-level warpage, which impacts the tacking and pre-bond yield due to extensive die drop-off du...

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Bibliographic Details

Published in:	2024 IEEE 74th Electronic Components and Technology Conference (ECTC) pp. 62 - 68
Main Authors:	Rao, B.S.S. Chandra, Kumar, Mishra Dileep, Sekhar, Vasarla Nagendra, Daniel, Ismael Cereno, Tippabhotla, Sasi Kumar, Chong, Ser Choong, C, Hemanth Kumar, Rao, Vempati Srinivasa
Format:	Conference Proceeding
Language:	English
Published:	IEEE 28-05-2024
Subjects:	Bonding C2W Hybrid Bonding Die-level warpage Dielectric measurement Dielectrics Leakage currents Silicon Stacking Three-dimensional displays Wafer bonding
Online Access:	Get full text
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