Dielectric Stack Optimization for Die-level Warpage Reduction for Chip-to-Wafer Hybrid Bonding

• Published in: 2024 IEEE 74th Electronic Components and Technology Conference (ECTC) pp. 62 - 68
• Main Authors: Rao, B.S.S. Chandra, Kumar, Mishra Dileep, Sekhar, Vasarla Nagendra, Daniel, Ismael Cereno, Tippabhotla, Sasi Kumar, Chong, Ser Choong, C, Hemanth Kumar, Rao, Vempati Srinivasa
• Format: Conference Proceeding
• Language: English
• Published: IEEE 28-05-2024
• Subjects: Bonding; C2W Hybrid Bonding; Die-level warpage; Dielectric measurement; Dielectrics; Leakage currents; Silicon; Stacking; Three-dimensional displays; Wafer bonding
• ISSN: 2377-5726
• DOI: 10.1109/ECTC51529.2024.00019

Chip-to-wafer hybrid bonding is a promising packaging technology for bumpless and high-density interconnection. However, this approach presents numerous challenges during die stacking, one of them is the die-level warpage, which impacts the tacking and pre-bond yield due to extensive die drop-off during the surface activation step of die tacking. This study focuses on the warpage measurement and its contribution from materials (dielectrics, Cu interconnection such as RDL, bond pad, and TSV) and optimizes the overall pre-bond 50um thick hybrid bonding die dielectric thickness such a way that the overall warpage <80um. Singulated 50um thick Si dies are fabricated using standard hybrid bonding integration flow and then plasma diced them for warpage measurements. Our findings reveal that Si dies with thicker SiCN film with high carbon content show a significant warpage and leakage current but superior interfacial bonding strength. On the other hand, low-carbon SiCN film shows lower interfacial bonding strength but better leakage current. Wafer to wafer bonding study confirmed that thickness SiCN can be as low as 20nm for bonding strength, however, achieving uniform SiCN thickness on pattern die is challenging due to soft film.