Effect of parasitic inductances on the switching responses of eGaN HEMTs

• Published in: 2022 IEEE International Conference on Electrical Sciences and Technologies in Maghreb (CISTEM) Vol. 4; pp. 1 - 6
• Main Authors: Wali, Khalil, Ghorbal, Manel Jebali Ben, Naouar, Mohamed Wissem, Ouali, Houssem
• Format: Conference Proceeding
• Language: English
• Published: IEEE 26-10-2022
• Subjects: Bridge circuits; GaN based high-electron-mobility transistors (HEMT); GaN modeling; HEMTs; Inductance; Layout; parasitic inductance; Switches; Transistors; Voltage; Wide Bandgap devices
• DOI: 10.1109/CISTEM55808.2022.10043917

Compared to Silicon (Si) transistors, Gallium Nitride (GaN) transistors offer superior features and advantages. In fact, GaN transistors have better performances in terms of thermal capacity, switching frequency range, switching losses, power rating, etc. Therefore, they can be considered as an appropriate solution for high power density energy conversion systems. In return, they are subjected to several challenges like the necessity to reduce parasitic inductances resulting from the layout of power converters. With the addition of the inherent GaN inductances, a non optimized power converter layout can lead to important voltage ringing and increased power losses. This is mainly due to the high dv/dt across GaN transistors during the switching process. In this context, this paper studies the effect of parasitic inductances on the switching responses of a half bridge converter. The considered converter is built using enhancement mode GaN based High Electron Mobility Transistors (eGaN-HEMTs) and is tested through a Double Pulse Test (DPT) under LTspice software. To show the great effect of parasitic inductances, two model levels were simulated and compared. The first one does not include any parasitic inductances while the second one is a complete model that includes the internal eGaN-HEMTs parasitic inductances in addition to the external ones related to the half bridge converter layout. Simulation tests considering the cases of optimized and non-optimized layouts were analyzed and compared to demonstrate the need for a layout optimization in order to minimize external parasitic inductances.