Using the New VPMADD Instructions for the New Post Quantum Key Encapsulation Mechanism SIKE

• Published in: 2019 IEEE 26th Symposium on Computer Arithmetic (ARITH) pp. 215 - 218
• Main Authors: Kostic, Dusan, Gueron, Shay
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-06-2019
• Subjects: Computer architecture; Encapsulation; NIST; Optimization; post quantum cryptography; Proposals; Quantum computing; Registers; software optimization; supersingular isogeny; VPMADD processor instructions
• ISSN: 2576-2265
• DOI: 10.1109/ARITH.2019.00050

This paper demonstrates the use of new processor instructions VPMADD, intended to appear in the coming generation of Intel processors (codename "Cannon Lake"), in order to accelerate the newly proposed key encapsulation mechanism (KEM) named SIKE. SIKE is one of the submissions to the NIST standardization process on post-quantum cryptography, and is based on pseudo-random walks in supersingular isogeny graphs. While very small keys are the main advantage of SIKE, its extreme computational intensiveness makes it one of the slowest KEM proposals. Performance optimizations are needed. We address here the "Level 1" parameters that target 64-bit quantum security, and deemed sufficient for the NIST standardization effort. Thus, we focus on SIKE503 that operates over Fp2 with a 503-bit prime p. These short operands pose a significant challenge on using VPMADD effectively. We demonstrate several optimization methods to accelerate Fp, Fp2, and the elliptic curve arithmetic, and predict a potential speedup by a factor of 1.72x.