Configurable hardware implementation of a pipelined DNLMS adaptive filter

• Published in: 2014 26th International Conference on Microelectronics (ICM) pp. 9 - 12
• Main Authors: Lee, Raymond, Khalid, Mohammed A. S., Abdel-Raheem, Esam
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-12-2014
• Subjects: Adaptation models; Adaptive filters; Cascading style sheets; echo cancellation; Echo cancellers; Field programmable gate arrays; Finite impulse response filters; FPGA; Hardware
• ISSN: 2159-1660
• DOI: 10.1109/ICM.2014.7071793

The delayed normalized least-mean-square (DNLMS) adaptive filtering algorithm is suitable for implementing pipelined architectures. Though previous literature has provided such architectures for DNLMS adaptive filters, none have given a detailed implementation. This paper presents the configurable hardware implementation of a pipelined, modular, low-latency, portable DNLMS adaptive filter which is tested for echo cancellation. The design is implemented onto the Altera Stratix FPGA and has a maximum operating frequency of 32.27 MHz. The design methodology consists of architectural derivation, fixed-point and RTL simulations, physical synthesis, and real-time hardware.