Fast computation of substrate resistances in large circuits

• Published in: Proceedings ED&TC European Design and Test Conference pp. 560 - 565
• Main Authors: van Genderen, A.J., van der Meijs, N.P., Smedes, T.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 1996
• Subjects: Analog integrated circuits; Circuit noise; Circuit simulation; Coupling circuits; Integrated circuit interconnections; Integrated circuit noise; Semiconductor device noise; Substrates; Voltage; Wire
• ISBN: 9780818674242; 0818674245
• ISSN: 1066-1409; 2377-6323
• DOI: 10.1109/EDTC.1996.494356

In this paper, we describe a method to quickly and accurately estimate substrate coupling effects in analog and mixed digital/analog integrated circuits. Unlike numerical methods, that can be used for circuits containing only a few hundreds of substrate terminals, the new method can quickly extract circuits containing many thousands of substrate terminals. Examples are given that show that the method is sufficiently accurate for practical circuit verification. The method has been implemented in the layout-to-circuit extractor Space.