An energy-efficient memory-based high-throughput VLSI architecture for convolutional networks

• Published in: 2015 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP) pp. 1037 - 1041
• Main Authors: Mingu Kang, Gonugondla, Sujan K., Min-Sun Keel, Shanbhag, Naresh R.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-04-2015
• Subjects: Arrays; Computational modeling; Compute memory; Convolutional networks; Delays; Machine learning; Pattern recognition; Random access memory; Registers; Throughput
• ISSN: 1520-6149; 2379-190X
• DOI: 10.1109/ICASSP.2015.7178127

In this paper, an energy efficient, memory-intensive, and high throughput VLSI architecture is proposed for convolutional networks (C-Net) by employing compute memory (CM) [1], where computation is deeply embedded into the memory (SRAM). Behavioral models incorporating CM's circuit non-idealities and energy models in 45nm SOI CMOS are presented. System-level simulations using these models demonstrate that the probability of handwritten digit recognition P r > 0.99 can be achieved using the MNIST database [2], along with a 24.5× reduced energy delay product, a 5.0× reduced energy, and a 4.9× higher throughput as compared to the conventional system.