Defect localization using physical design and electrical test information

• Published in: 2000 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 2000 (Cat. No.00CH37072) pp. 108 - 115
• Main Authors: Stanojevic, Z., Balachandran, H., Walker, D.M.H., Lakhani, F., Jandhyala, S.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2000
• Subjects: Automatic test pattern generation; Circuit faults; Circuit testing; Failure analysis; Fault diagnosis; Inspection; Instruments; Logic testing; Scanning electron microscopy; System testing
• ISBN: 9780780359215; 0780359216
• ISSN: 1078-8743; 2376-6697
• DOI: 10.1109/ASMC.2000.902568

In this work we describe an approach of using physical design and test failure knowledge to localize defects in random logic. We term this approach computer-aided fault to defect mapping (CAFDM). An integrated tool has been developed on top of an existing commercial ATPG tool. CAFDM was able to correctly identify the defect location and layer in all 9 of the chips that had bridging faults injected via FIB. Preliminary failure analysis results on production defects are promising.