A toolset for the analysis and optimization of motion estimation algorithms and processors

• Published in: 2009 International Conference on Field Programmable Logic and Applications pp. 423 - 428
• Main Authors: Spiteri, T., Vafiadis, G., Nunez-Yanez, J.L.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-08-2009
• Subjects: Algorithm design and analysis; Computer architecture; Design optimization; Hardware; Motion estimation; Process design; Rate-distortion; Space exploration; Systolic arrays; Testing
• ISSN: 1946-147X; 1946-1488
• DOI: 10.1109/FPL.2009.5272247

This paper presents a reconfigurable processor designed to execute user-defined block-matching motion estimation algorithms, and a toolset for the design of such algorithms and for the configuration of the processor. The toolset enables the exploration of the processor's design space in order to find an optimal configuration depending on the target application. The use of the toolset to test different configurations for different kinds of video sequences is illustrated. Experimental results show the benefits and cost of certain optimizations in the motion estimation process, and that fast block-matching search algorithms can outperform full search algorithms commonly used in hardware implementations. The usefulness of the toolset in exploring the configuration space is also shown.