Dynamic voltage and cache reconfiguration for low power

• Published in: Proceedings Design, Automation and Test in Europe Conference and Exhibition Vol. 2; pp. 1376 - 1377 Vol.2
• Main Authors: Nacul, A.C., Givargis, T.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2004
• Subjects: Dynamic voltage scaling; Embedded system; Frequency; Heuristic algorithms; Potential energy; Processor scheduling; Scheduling algorithm; Timing; Voltage control; Writing
• ISBN: 0769520855; 9780769520858
• ISSN: 1530-1591; 1558-1101
• DOI: 10.1109/DATE.2004.1269096

This article deals about dynamic voltage and cache reconfiguration online algorithm that dynamically adapts the processor speed and the cache subsystem to the workload requirements for the purpose of saving energy. The workload is considered to be a set of tasks with real-time deadlines. Our online algorithm is invoked as part of the OS scheduler, which performs standard earliest deadline first(EDF)task scheduling first. Then, our online algorithm, determines an ideal voltage/cache configuration for the current executing task.