A 100-GbE reverse gearbox IC in 40nm CMOS for supporting legacy 10- and 40-GbE standards

• Published in: 2015 Symposium on VLSI Circuits (VLSI Circuits) pp. C212 - C213
• Main Authors: Yoon, Taehun, Lee, Joon-Yeong, Han, Kwangseok, Lee, Jeongsup, Lee, Sangeun, Kim, Taeho, Won, Hyosup, Park, Jinho, Bae, Hyeon-Min
• Format: Conference Proceeding Journal Article
• Language: English
• Published: jsap 01-06-2015
• Subjects: 100-GbE; CDR; Circuits; Clocks; CMOS; CMOS integrated circuits; CMOS technology; Gearboxes; Integrated circuits; Jitter; Legacy; MLG 2.0; Phase locked loops; Power consumption; Reverse gearbox IC; Synchronization; transceiver
• ISBN: 9784863485020; 4863485026
• ISSN: 2158-5601; 2158-5636
• DOI: 10.1109/VLSIC.2015.7231262

This paper presents the industry's first low-power 100-Gigabit Ethernet (GbE) multi-link gearbox (MLG) IC, which facilitates transport of independent 10-GbE and 40-GbE signals to 4×25G physical layers implementing 100GBASE-R. The IC consumes only 1.37-W while implementing complicated reverse gearbox functionality. The measured TX jitter from the 25-Gb/s lane is 1.6-ps rms , and the recovered clock jitter is 0.5-ps rms . The measured RX input sensitivity for a BER 10 -12 is 42-mV ppd . The proposed gearbox IC, fabricated in a 40nm CMOS process, occupies 3.7×3.4-mm 2 . The power consumption of RX and TX in 25G interfaces are 47-mW and 51-mW, respectively, and those of a 10G interfaces are 24-mW and 25-mW, respectively. Gearbox functionalities are verified with embedded self-test logics.