A 15.5-mW 20-GSps 4-bit charge-steering flash ADC

• Published in: 2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) pp. 1 - 4
• Main Authors: Ayesh, Mostafa M., Ibrahim, Sameh, Aboudina, Mohamed M.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-08-2015
• Subjects: ADC-based systems; Ash; Capacitors; Charge Steering; Clocks; CMOS integrated circuits; Flash ADC; High-speed ADC; Latches; Power demand; Preamplifier; Receivers; Time-interleaved
• ISSN: 1548-3746; 1558-3899
• DOI: 10.1109/MWSCAS.2015.7282153

This paper presents a 4-bit 20-GSps time-interleaved flash ADC for an ADC-based high-speed serial-link equalizer. The ADC is designed and simulated in a 65-nm CMOS technology. It dissipates 15.5 mW from a 1-V supply while operating at 20 GSps. Low power consumption is achieved by utilizing charge-steering concept, sharing single reference ladder across all the four interleaved branches, and merging the dynamic latch into the pre-amplifier of the comparator. Results show that for a sinusoidal input frequency of 9.84 GHz with an amplitude of 600 mV diff , the SNDR of the digital output is 23.9 dB, SFDR is 33.6 dB, and the effective number of bits (ENOB) is 3.67 bits.