Testing Real-Time Embedded Systems with Hardware-in-the-Loop Simulation Using High Level Architecture

• Published in: 2015 Brazilian Symposium on Computing Systems Engineering (SBESC) pp. 142 - 147
• Main Authors: Vieira S. Junior, Jose Claudio, Brito, Alisson V., Nascimento, Tiago P.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-11-2015
• Subjects: Computational modeling; Computer architecture; Embedded systems; Hardware; Hardware-in-the-Loop; High-Level Architecture; Real-Time; Real-time systems; Synchronization; Testing
• ISSN: 2324-7894
• DOI: 10.1109/SBESC.2015.34

This work presents a technique for testing real-time embedded systems using Hardware-in-the-Loop (HIL) simulation, exploiting High-Level Architecture (HLA) standard for interoperability and synchronization of heterogeneous architectures. The proposed testing approach uses the Ptolemy framework to verify in real-time models running in hardware against their respective reference models developed in Ptolemy. The approach consisted in the development of new actors in Ptolemy responsible for the integration with HLA and the verification process, and a software interface to be deployed in the hardware under verification. As proof of concept, the proposed approach was applied for the testing of a simple mobile robot navigation algorithm. All data collected by sensors and the respective reactions are transferred in real-time to Ptolemy, which performs the verification against a reference model. Such technique allows different Models of Computation (MoC) to be used as reference models in Ptolemy to verify different hardware architectures synchronously based on HLA.