Multi-granular Arithmetic in a Coarse-Grain Reconfigurable Architecture

• Published in: 2016 Euromicro Conference on Digital System Design (DSD) pp. 599 - 606
• Main Authors: Louwers, Stef, Waeijen, Luc, Wijtvliet, Mark, Koolen, Ruud, Corporaal, Henk
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-08-2016
• Subjects: Adders; BLOCKS; CGRA; Computer architecture; Decoding; Energy Efficiency; Field programmable gate arrays; Hardware; Logic gates; Multi-Granular Arithmetic; Multiplication; Registers
• DOI: 10.1109/DSD.2016.98

Mismatch between operand width and hardware operation width is a source of energy inefficiency. This work proposes multi-granular arithmetic, which can adapt the hardware operation width to the application, preventing energy being wasted. In particular multi-granular arithmetic in the context of coarse-grain reconfigurable architectures is considered for the operations of addition, accumulation, multiplication, and multiply-accumulation. Using a silicon synthesis-toolflow it is shown that the multi-granular designs can perform narrow width operations, e.g. an 8-by-8 multiplication, much more efficiently than standard full-width circuits. For multiplication the required energy is reduced by up to 15 times under realistic conditions when compared to a full-width 32x32 multiplier.