A new ATPG algorithm to limit test set size and achieve multiple detections of all faults

• Published in: Design, Automation, and Test in Europe: Proceedings of the conference on Design, automation and test in Europe; 04-08 Mar. 2002 pp. 94 - 99
• Main Authors: Sooryong Lee, Cobb, B., Dworak, J., Grimaila, M.R., Mercer, M.R.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2002
• Subjects: Automatic test pattern generation; Circuit faults; Circuit testing; Compaction; Electrical fault detection; Fault detection; Manufacturing; Predictive models; System testing; Test pattern generators
• ISBN: 0769514715; 9780769514710
• ISSN: 1530-1591; 1558-1101
• DOI: 10.1109/DATE.2002.998255

Deterministic observation and random excitation of fault sites during the ATPG process dramatically reduces the overall defective part level. However, multiple observations of each fault site lead to increased test set size and require more tester memory. In this paper we propose a new ATPG algorithm to find a near-minimal test pattern set that detects faults multiple times and achieves excellent defective part level. This greedy approach uses 3-value fault simulation to estimate the potential value of each vector candidate at each stage of ATPG. The result shows generation of a close to minimal vector set is possible only using dynamic compaction techniques in most cases. Finally, a systematic method to trade-off between defective part level and test size is also presented.