Agile-DRAM: Agile Trade-Offs in Memory Capacity, Latency, and Energy for Data Centers

• Published in: 2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA) pp. 1141 - 1153
• Main Authors: Lee, Jaeyoon, Jung, Wonyeong, Kim, Dongwhee, Kim, Daero, Lee, Junseung, Kim, Jungrae
• Format: Conference Proceeding
• Language: English
• Published: IEEE 02-03-2024
• Subjects: Access Latency; Data centers; DRAM; Memory; Memory management; Power Consumption; Power demand; Random access memory; Refresh; Runtime; Sensitivity; System performance
• ISSN: 2378-203X
• DOI: 10.1109/HPCA57654.2024.00089

Data centers frequently face significant memory under-utilization due to factors such as infrastructure overprovisioning, inefficient workload scheduling, and limited server configurations. This paper introduces Agile-DRAM, a novel DRAM architecture that addresses this issue by flexibly converting the under-utilized memory capacity into enhanced latency performance and reduced power consumption. Through minor modifications to the conventional DRAM architecture, Agile-DRAM supports multiple operational modes: low-latency, lowpower, and the default max-capacity mode. Notably, Agile-DRAM facilitates agile transitions between these modes in response to workload fluctuations in data centers at runtime. Evaluation results demonstrate that the low-latency mode can boost singlecore execution speed by up to 25.8% and diminish energy usage by up to 22.4%. Similarly, the low-power mode can reduce DRAM standby and self-refresh power by 31.6% and 85.7%, respectively.