Comprehensive Design and Analysis of Fan-Out Wafer Level Package

• Published in: 2019 IEEE 21st Electronics Packaging Technology Conference (EPTC) pp. 107 - 110
• Main Authors: Zhang, Xiaowu, Andriani, Yosephine, Jong, Ming Chinq, Bu, Lin, Lau, Boon Long, Boon, Simon Lim Siak, Siang, Sharon Lim Pei, Han, Yong, Liu, Songlin, Wang, Xiaobai
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-12-2019
• Subjects: Guidelines; Packaging; Predictive models; Semiconductor device modeling; Semiconductor device reliability; Wafer scale integration
• DOI: 10.1109/EPTC47984.2019.9026620

This paper presents an advanced modeling technology on wafer warpage after post mold curing (PMC) for the 12 inch mold-1 st Fan-Out Wafer Level Packaging (FOWLP) with consideration of effects of viscoelastic model and chemical cure shrinkage, and layer design of the mold-1 st packages. Results show that warpage of mold-1 st FOWLP wafer predicted by the advanced modeling technology agrees well with the experimental result. A new guideline for FOWLP process flow is provided as well, which will be useful to the packaging industry. The advantages of the new guideline for FOWLP process flow are: (1) to eliminate wafer warpage correction process and save a lot of cost and time; (2) to serve as a basis for process selection to meet the trends and needs of a reliable fan-out wafer level package with lower wafer warpage during FOWLP wafer process; and (3) to be important to enhance survivability during wafer process and thin-wafer handling.