Wafer Level Void-Free Molded Underfill for High-Density Fan-out Packages

• Published in: 2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) pp. 419 - 424
• Main Authors: Mok, InSu, Bae, JaeHun, Ki, WonMyoung, Yoo, HoDol, Ryu, SeungMan, Kim, SooHyun, Jung, GyuIck, Hwang, TaeKyeong, Do, WonChul
• Format: Conference Proceeding
• Language: English
• Published: IEEE 02-12-2020
• Subjects: compression mold; Compression molding; Electromagnetic compatibility; High-Density Fan-Out; Image edge detection; Inspection; mold flow simulation; Semiconductor device modeling; Simulation; Viscosity; Wafer Level Packaging; wafer-level MUF
• DOI: 10.1109/EPTC50525.2020.9315128

In this study, experiments and mold flow simulation results are presented for a void-free wafer level molded underfill (WLMUF) process with High-Density Fan-Out (HDFO) test vehicles using a wafer-level compression molding process. The redistribution layer (RDL)-first technology was applied with 3 layers of a fine-pitch RDL structure. The test samples comprised 11.5 \times 12.5-\text{mm}^{2} die with tall copper (Cu) pillars around the die. Destructive analysis was used to clearly inspect MUF voids on the whole wafer area. The molded wafer was ground to the bump area where the MUF voids exist using a mold grinding machine and MUF voids were inspected through a high-resolution scope. The WLMUF characteristics of the conventional compression molding process with various epoxy molding compound (EMC) types have been investigated. A void-free WLMUF process was achieved by applying an optimized EMC dispensing method and parameters. These results are verified through the mold flow simulation, which correlated to the experimental results. Finally, the void-free WLMUF HDFO samples passed reliability tests of temperature cycling (TC), high temperature storage (HTS) and Unbiased Highly Accelerated Stress Test (UHAST) after moisture resistance test (MRT) Level 3.