Can We Ever Get to a 100 nm Tall Library? Power Rail Design for 1nm Technology Node

• Published in: 2020 IEEE Symposium on VLSI Technology pp. 1 - 2
• Main Authors: Moroz, V., Lin, X. W., Asenov, P., Sherlekar, D., Choi, M., Cheng, B., Parikh, S., Chan, Po-Wen, Lee, J. J.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-06-2020
• Subjects: Libraries; Metals; Rails; Resistance; Routing; Transistors; Wires
• ISSN: 2158-9682
• DOI: 10.1109/VLSITechnology18217.2020.9265022

We explore six different PR (Power Rail) design options in the range of library cell heights from 100 nm to 130 nm for the 1nm design rules (i.e. CPP (Contacted Poly Pitch) of 40 nm and minimum MP (Metal Pitch) of 20 nm). All these design options include 4 tracks for signal routing but different width of the power rails, ranging from conventional power rail design to the power rails having larger thickness than the signal wires on the same metal layer; BPR (Buried Power Rails); and a combination of the conventional and buried power rails. Ru (ruthenium) and Mo (molybdenum) metals with subtractive process (i.e. deposit and etch instead of the damascene process) are considered for both the power rail and the signal routing. The six technology/design options are benchmarked based on PPA (Power-Performance-Area) analysis of a routed GPU (Graphics Processing Unit) logic block operated at HP (High Performance).