Test resource optimization for multi-site testing of SOCs under ATE memory depth constraints

• Published in: Proceedings - International Test Conference pp. 1159 - 1168
• Main Authors: Iyengar, V., Goel, S.K., Marinissen, E.J., Chakrabarty, K.
• Format: Conference Proceeding
• Language: English
• Published: Piscataway NJ IEEE 2002
• Subjects: Applied sciences; Constraint optimization; Cost function; Design. Technologies. Operation analysis. Testing; Electronics; Embedded computing; Exact sciences and technology; Hardware; Integrated circuits; Laboratories; Logic testing; Memory management; Microelectronics; Routing; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Wire; Computer hardware; Integrated circuit testing; Integrated circuit; Testing equipment; Scheduling; System on a chip; Bus(channel); Optimization
• ISBN: 9780780375420; 0780375424
• ISSN: 1089-3539; 2378-2250
• DOI: 10.1109/TEST.2002.1041874

We present a two-step solution to the problem of test resource optimization for multi-site testing of embedded-core-based SOCs. In step 1, an efficient technique based on enhanced rectangle packing is used to design the wrapper/TAM (test access mechanisms) architecture such that the SOC test suite fits in a single ATE memory load. Furthermore, the total TAM width for the SOC is minimized, thereby reducing routing complexity and hardware cost. Minimum TAM width directly leads to the minimization of the number of ATE channels used, thus enabling multi-site testing. In step 2, test scheduling is performed such that "idle" bits appearing between core tests on ATE channels are moved to the end of each channel. This reduces the memory depth allocated to the channels from the pool of ATE memory. The saved memory can be mapped to the remaining ATE channels to test other SOCs, thereby further facilitating multi-site testing. We present experimental results on our technique for five benchmark SOCs.