Leakage Current Compensation in Large Number of Inactive Synapses in a 130nm CMOS Process

• Published in: 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS) pp. 460 - 463
• Main Authors: Hasan, Md Munir, Holleman, Jeremy
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-08-2020
• Subjects: Leakage currents; Logic gates; MOS devices; Synapses; Transistors
• ISSN: 1558-3899
• DOI: 10.1109/MWSCAS48704.2020.9184611

Hardware implementations of neuromorphic circuits have been limited mostly in technology nodes that are much older than more advanced CMOS technology nodes available during the time of fabrication. This is mainly because leakage currents increase substantially with down scaling. Neuromorphic computational elements are mostly made of subthreshold current mode circuits. At smaller advanced technology nodes, the leakage currents become comparable to the current levels at which the circuits are designed to operate. This is particularly problematic when a large number of synapses connected to a neuron conduct current when they are supposed to be at off state. Having a workaround to the current leakage problem could enable us to design small footprint circuits in smaller technology nodes. In this paper, we propose a technique to compensate the leakage currents from a large number of synapses in a 130nm CMOS process. We present transistor level simulation results to show the viability of the technique.