Distributed Hardware Accelerated Secure Joint Computation on the COPA Framework

• Published in: 2022 IEEE High Performance Extreme Computing Conference (HPEC) pp. 1 - 7
• Main Authors: Patel, Rushi, Haghi, Pouya, Jain, Shweta, Kot, Andriy, Krishnan, Venkata, Varia, Mayrmk, Herbord, Martin
• Format: Conference Proceeding
• Language: English
• Published: IEEE 19-09-2022
• Subjects: Bandwidth; Data transfer; Libraries; Multi-party computation; Protocols; Software algorithms; Throughput
• ISSN: 2643-1971
• DOI: 10.1109/HPEC55821.2022.9926388

Performance of distributed data center applications can be improved through use of FPGA-based SmartNICs, which provide additional functionality and enable higher bandwidth communication and lower latency. Until lately, however, the lack of a simple approach for customizing SmartNICs to application requirements has limited the potential benefits. Intel's Configurable Network Protocol Accelerator (COPA) provides a customizable FPGA framework that integrates both hardware and software development to improve computation and commu-nication performance. In this first case study, we demonstrate the capabilities of the COPA framework with an application from cryptography - secure Multi-Party Computation (MPC) - that utilizes hardware accelerators connected directly to host memory and the COPA network. We find that using the COPA framework gives significant improvements to both computation and communication as compared to traditional implementations of MPC that use CPUs and NICs. A single MPC accelerator running on COPA enables more than 17Gb/s of communication bandwidth while using only 3% of Stratix 10 resources. We show that utilizing the COPA framework enables multiple MPC accelerators running in parallel to fully saturate a 100Gbps link enabling higher performance compared to traditional NICs.