Low temperature backside damascene processing on temporary carrier wafer targeting 7μm and 5μm pitch microbumps for N equal and greater than 2 die to wafer TCB stacking

• Published in: 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) pp. 1108 - 1113
• Main Authors: Derakhshandeh, Jaber, Beyne, Eric, Beyer, Gerald, Capuz, Giovanni, Cherman, Vladimir, De Preter, Inge, Gerets, Carine, Shafahian, Ehsan, Kennes, Koen, Jamieson, Geraldine, Cochet, Tom, Webers, Tomas, Tobback, Bert, Van der Plas, Geert, La Tulipe, Douglas Charles, Phommahaxay, Alain, Miller, Andy
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-05-2022
• Subjects: 3D die to wafer stacking; Electronic components; intermetallic compound; Low temperature damascene processing on wafer BS; Materials reliability; Performance evaluation; Plating; Semiconductor device reliability; spacer and solder bumps; Stacking; TBM (temporary bonding material); TCB; Wafer bonding; wafer to wafer bonding
• ISSN: 2377-5726
• DOI: 10.1109/ECTC51906.2022.00179

In this paper, for first time, damascene process on thinned and bonded device wafer to a carrier using TBM layer is introduced. All the BS process steps including, dielectric depositions, etching, seed/barrier deposition, plating and CMP are performed at temperatures within the thermal budget of TBM layer. FIB images show no impact of BS processing on FS bumps. This process is done on a test vehicle with 20, 10, 7 and 5um pitch structures in F2F and B2F (or F2B) forms, where good electrical data, good solder joint formation and good reliability performance is obtained.