Generation of oxide traps in Back-Side-Illuminated CMOS Image Sensors and impact on reliability

Generation of oxide traps in Back-Side-Illuminated CMOS Image Sensors and impact on reliability

A systematic characterization of peripheral transistors in Front-Side and Back-Side-Illuminated CMOS Image Sensors is presented. Experimental results are supported by electrostatic simulations of the gate stack. The out-coming picture is that a distribution of border traps is generated in the gate o...

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Bibliographic Details
Published in:ESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC) pp. 234 - 237
Main Authors: Vici, Andrea, Russo, Felice, Lovisi, Nicola, Marchioni, Aldo, Casella, Antonio, Irrera, Fernanda
Format: Conference Proceeding
Language:English
Published: IEEE 01-09-2019
Online Access:Get full text
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Summary:A systematic characterization of peripheral transistors in Front-Side and Back-Side-Illuminated CMOS Image Sensors is presented. Experimental results are supported by electrostatic simulations of the gate stack. The out-coming picture is that a distribution of border traps is generated in the gate oxide in the Back-Side configuration during the wafer flipping/bonding/thinning and via opening loop. It shifts the flatband voltage, increases the channel leakage current and alters the oxide electric field. Different reliability tests demonstrate that in the Back-Side-Illuminated configuration lifetime is degraded respect to the Front-Side one, due to the particular features of that trap distribution.
ISSN:2378-6558
DOI:10.1109/ESSDERC.2019.8901726