Design of BIST(Built-In-Self-Test)Embedded Master-Slave communication using SPI Protocol

• Published in: 2021 3rd International Conference on Signal Processing and Communication (ICPSC) pp. 581 - 585
• Main Authors: Jose, Bitty, Immanuel, J. Samson
• Format: Conference Proceeding
• Language: English
• Published: IEEE 13-05-2021
• Subjects: BIST; Built-in self-test; Complexity theory; Data transfer; Hardware; Maintenance engineering; Master-slave; MISO; MOSI; ORA; Signal processing; SPI; TPG
• DOI: 10.1109/ICSPC51351.2021.9451702

The Serial-Peripheral Interface(SPI) Protocol also called as synchronous serial interface specification is used for communication between single master and single/multiple slaves. With the increase in number of slaves causing high complexity of circuit creates a demand in self testability feature for SPI module in order to test for fault free circuits. Built-In-Self-Test(BIST) is the answer for self-test in circuits as well as it helps in reduction of maintenance and testing cost. Design of BIST embedded SPI module with Single Master and Single Slave configuration has been introduced in this paper, here 8-bit data is transferred across the module ,where the circuit under test(CUT) is being self-tested with BIST feature for it's correctness. This SPI module is designed using Verilog Hardware Description Language(HDL) using EDA playground platform for applications like Application Specific Integrated Circuit(ASIC)or System on Chip(SOC).