A Single-Chip 25.3-28.0 GHz SiGe BiCMOS PLL with −134 dBc/Hz Phase Noise at 10 MHz Offset and −96 dBc Reference Spurs

A Single-Chip 25.3-28.0 GHz SiGe BiCMOS PLL with −134 dBc/Hz Phase Noise at 10 MHz Offset and −96 dBc Reference Spurs

This paper presents a 25.3-28.0 GHz integer-N PLL in a 90 nm SiGe BiCMOS process. The PLL heavily utilizes SiGe HBTs for high-speed and low-noise operation, featuring −96 dBc reference spurs and −97/−107/−134 dBc/Hz phase noise at 1 kHz / 1 MHz / 10 MHz offset. The PLL has 94 fs integrated jitter at...

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Bibliographic Details
Published in:2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS) pp. 1 - 4
Main Authors: Hickle, Mark D., Grout, Kevin, Grens, Curtis, Flewelling, Gregory, Turner, Steven Eugene
Format: Conference Proceeding
Language:English
Published: IEEE 05-12-2021
Subjects:
BiCMOS
BiCMOS integrated circuits
Electronic warfare
frequency synthesis
Integrated circuits
Jitter
Phase locked loops
Phase noise
Radar applications
Transceivers
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Summary:This paper presents a 25.3-28.0 GHz integer-N PLL in a 90 nm SiGe BiCMOS process. The PLL heavily utilizes SiGe HBTs for high-speed and low-noise operation, featuring −96 dBc reference spurs and −97/−107/−134 dBc/Hz phase noise at 1 kHz / 1 MHz / 10 MHz offset. The PLL has 94 fs integrated jitter at a 26 GHz carrier frequency and draws 850 mW from a 3.3V supply for a jitter-power FOM of −231 dBc. The PLL has lower reference spurs and phase noise at 1 kHz and 10 MHz offsets compared to recently published mmW PLLs, making this PLL well-suited for high dynamic range transceiver applications.
DOI:10.1109/BCICTS50416.2021.9682458